A controller area network (CAN) is a communication bus, communication standard, and set of hardware used in vehicles which allows multiple separate nodes to communicate with one another. The CAN transceiver is the interface circuit that connects the CAN bus with the CAN microcontroller or microprocessor (μC/μP).
A CAN bus has CAN high (CANH) and CAN low (CANL) nodes or lines. The difference in voltage between these two lines (Vdiff)=CANH−CANL and this determines the state of the bus. Vdiff>0.9V is defined as a dominant (DOM) state. Vdiff<0.5V is defined as a recessive (REC) state.
The transceiver receives a digital signal from the μC through its CANTXD input pin. The transceiver transmits this signal onto the bus through a transmit circuit and observes the state of the bus through a receiver circuit which then sends a signal back to the μC through the CANRXD output pin. The state of CANTXD and CANRXD are defined as DOM if they are logic 0 and are defined as REC if they are a logic 1. Data is transmitted by transmitting a series of bits via a signal comprising a series of pulses, where high state represents a logic “1” (REC) and low state a logic “0” (DOM).
CAN communication speeds are limited by the capabilities of the CAN bus and CAN transceiver. ISO 11898-2 standardizes hardware bit timing requirements for CAN transceivers for flexible data (CAN FD) rates up to 5 MB/S. Specifically, ISO 11898-2 defines the allowed minimum and maximum width of a single REC state on the bus (Tbit(bus)), at the transceiver CANRXD pin (Tbit(rxd)), and the symmetry of these two parameters (dTrec=Tbit(rxd)−Tbit(bus)). These parameters are a function of CAN data rates and will therefore have to be changed when CAN data rates inevitably increase beyond 5 MB/S. Therefore, transceiver hardware must continually evolve with increasing CAN data rates since the requirements for higher date rates are not standardized in advance.
Complicating the problem is that wave-shaping of CANH and CANL bus slew on and slew off is required to meet electromagnetic compatibility (EMC) requirements. EMC requirements must be met regardless of the data rate. Wave-shaping slows down the Vdiff transitions and therefore impacts bit timing as the data rate increases.
Furthermore, advanced CAN transceivers are now defined by international standards and are available which are capable of processing CAN bus messages for the purpose of selective wakeup on frame (WUF) or so called partial networking (PN) CAN. Bit timing requirements must be met within the transceiver for it to correctly read CAN frames on the bus.
Tbit(bus), Tbit(rxd), dTrec, and wave-shaping can each independently vary with temperature and manufacturing process making it difficult to optimize all parameters with a single fixed design methodology. Furthermore, Tbit(bus), Tbit(rxd), and dTrec are defined by international standards organizations and are therefore only presently defined for existing CAN data rates. Future CAN data rates will require unknown Tbit(bus), Tbit(rxd), and dTrec parameters making it impossible for transceivers with a fixed (un-trimmable) design solution to adapt to changing standards.
U.S. Pat. No. 9,606,948B2 “CAN bus edge timing control for dominant-to-recessive transitions” describes a circuit for speeding up the DOM to REC transitions by actively driving the bus recessive as opposed to letting the bus decay through the RC bus load as is usually the case for CAN transceivers. U.S. Pat. No. 9,973,348B2 “Transceiver circuit and method for controller are networks” describes a circuit for selectively speeding up DOM to REC transitions when flexible data rates are present. U.S. Pat. Nos. 9,606,948B2 and 9,973,348B2 can reduce Tbit(bus) and Tbit(rxd) by the same value but cannot increase these parameters and cannot independently adjust these parameters. Furthermore, the solution inherently couples wave-shaping with bit timing parameters and therefore fails to meet the required solution.
It is an object of the invention to provide a CAN system which overcomes these problems. It is further an object to provide such a system which has which has flexibility in the selectivity of Tbit(bus), Tbit(rxd),